Some Zhaoxin CPUs declare support SSE4.2 instruction sets but having a CRC32C instruction implementation that not working as intended. Set low performance CRC32C flag on these CPUs for later use. Signed-off-by: LeoLiu-oc &lt;LeoLiu-oc(a)zhaoxin.com&gt; ---  arch/x86/kernel/cpu/centaur.c | 7 +++++++  arch/x86/kernel/cpu/zhaoxin.c | 7 +++++++  2 files changed, 14 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 49b33cc78751..1c92a57364e9 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -116,6 +116,13 @@ static void early_init_centaur(struct cpuinfo_x86 *c)          set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);      } +    /* +     * These CPUs declare support SSE4.2 instruction sets but +     * having low performance CRC32C instruction implementation. +     */ +    if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) +        set_cpu_cap(c, X86_FEATURE_CRC32C_LOW_PERF); +      if (c->cpuid_level >= 0x00000001) {          u32 eax, ebx, ecx, edx; diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index b6fc969b3e74..75fca076d9ab 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -85,6 +85,13 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)              c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);      } +    /* +     * These CPUs declare support SSE4.2 instruction sets but +     * having low performance CRC32C instruction implementation. +     */ +    if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b)) +        set_cpu_cap(c, X86_FEATURE_CRC32C_LOW_PERF); +      if (detect_extended_topology_early(c) < 0)          detect_ht_early(c);  } -- 2.20.1