SSE4.2 on Zhaoxin CPUs are compatible with Intel. The presence of CRC32C instruction is enumerated by CPUID.01H:ECX.SSE4_2[bit 20] = 1. Some Zhaoxin CPUs declare support SSE4.2 instruction sets but their CRC32C instruction are working with low performance. Add a synthetic CPU flag to indicates that the CRC32C instruction is not working as intended. This low performance CRC32C instruction flag is depend on X86_FEATURE_XMM4_2. Signed-off-by: LeoLiu-oc <LeoLiu-oc(a)zhaoxin.com> ---  arch/x86/include/asm/cpufeatures.h | 1 +  arch/x86/kernel/cpu/cpuid-deps.c   | 1 +  2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 77ecd7136536..653de364f36e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@  #define X86_FEATURE_CQM_MBM_LOCAL    (11*32+ 3) /* LLC Local MBM monitoring */  #define X86_FEATURE_FENCE_SWAPGS_USER    (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */  #define X86_FEATURE_FENCE_SWAPGS_KERNEL    (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ +#define X86_FEATURE_CRC32C_LOW_PERF        (11*32+ 6) /* "" Low performance */  /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */  #define X86_FEATURE_AVX512_BF16        (12*32+ 5) /* AVX512 BFLOAT16 instructions */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index a444028d8145..aebb5e92c31d 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -63,6 +63,7 @@ static const struct cpuid_dep cpuid_deps[] = {      { X86_FEATURE_CQM_MBM_TOTAL,    X86_FEATURE_CQM_LLC   },      { X86_FEATURE_CQM_MBM_LOCAL,    X86_FEATURE_CQM_LLC   },      { X86_FEATURE_AVX512_BF16,    X86_FEATURE_AVX512VL  }, +    { X86_FEATURE_CRC32C_LOW_PERF,    X86_FEATURE_XMM4_2  },      {}  }; -- 2.20.1