24 Mar
2021
24 Mar
'21
2:30 p.m.
From: Xie XiuQi <xiexiuqi(a)huawei.com>
commit 4636eb70b3e31067da05c789c84f5fcbabde6770 openEuler-1.0
hulk inclusion
category: feature
bugzilla: 5510
CVE: NA
Signed-off-by: Xie XiuQi <xiexiuqi(a)huawei.com>
Reviewed-by: Hanjun Guo <guohanjun(a)huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com>
Signed-off-by: Xin Hao <haoxing990(a)gmail.com>
---
arch/arm64/include/asm/mpam.h | 22 +++++++++++++++++++++-
arch/arm64/include/asm/mpam_sched.h | 18 +++++++++---------
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/mpam.h b/arch/arm64/include/asm/mpam.h
index 61bca6334850..fb787e34145b 100644
--- a/arch/arm64/include/asm/mpam.h
+++ b/arch/arm64/include/asm/mpam.h
@@ -20,7 +20,7 @@
#define SYS_MPAMVPMn_EL2(n) sys_reg(3, 4, 10, 6, n)
#define SYS_MPAMIDR_EL1 sys_reg(3, 0, 10, 4, 4)
-#define MPAM_MASK(n) ((1 << n) - 1)
+#define MPAM_MASK(n) ((1UL << n) - 1)
/* plan to use GENMASK(n, 0) instead */
/*
@@ -45,6 +45,26 @@
#define PMG_I_SHIFT (PARTID_D_SHIFT + PARTID_BITS)
#define PMG_D_SHIFT (PMG_I_SHIFT + PMG_BITS)
+#define PARTID_I_MASK (PARTID_MASK << PARTID_I_SHIFT)
+#define PARTID_D_MASK (PARTID_MASK << PARTID_D_SHIFT)
+#define PARTID_I_CLR(r) ((r) & ~PARTID_I_MASK)
+#define PARTID_D_CLR(r) ((r) & ~PARTID_D_MASK)
+#define PARTID_CLR(r) (PARTID_I_CLR(r) & PARTID_D_CLR(r))
+
+#define PARTID_I_SET(r, id) (PARTID_I_CLR(r) | ((id) << PARTID_I_SHIFT))
+#define PARTID_D_SET(r, id) (PARTID_D_CLR(r) | ((id) << PARTID_D_SHIFT))
+#define PARTID_SET(r, id) (PARTID_CLR(r) | ((id) << PARTID_I_SHIFT) | ((id)
<< PARTID_D_SHIFT))
+
+#define PMG_I_MASK (PMG_MASK << PMG_I_SHIFT)
+#define PMG_D_MASK (PMG_MASK << PMG_D_SHIFT)
+#define PMG_I_CLR(r) ((r) & ~PMG_I_MASK)
+#define PMG_D_CLR(r) ((r) & ~PMG_D_MASK)
+#define PMG_CLR(r) (PMG_I_CLR(r) & PMG_D_CLR(r))
+
+#define PMG_I_SET(r, id) (PMG_I_CLR(r) | ((id) << PMG_I_SHIFT))
+#define PMG_D_SET(r, id) (PMG_D_CLR(r) | ((id) << PMG_D_SHIFT))
+#define PMG_SET(r, id) (PMG_CLR(r) | ((id) << PMG_I_SHIFT) | ((id) <<
PMG_D_SHIFT))
+
#define TRAPMPAM1EL1_SHIFT (PMG_D_SHIFT + PMG_BITS)
#define TRAPMPAM0EL1_SHIFT (TRAPMPAM1EL1_SHIFT + 1)
#define TRAPLOWER_SHIFT (TRAPMPAM0EL1_SHIFT + 13)
diff --git a/arch/arm64/include/asm/mpam_sched.h b/arch/arm64/include/asm/mpam_sched.h
index 53c3f29417ab..4e3d20950285 100644
--- a/arch/arm64/include/asm/mpam_sched.h
+++ b/arch/arm64/include/asm/mpam_sched.h
@@ -49,8 +49,8 @@ DECLARE_PER_CPU(struct intel_pqr_state, pqr_state);
static void __mpam_sched_in(void)
{
struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
- u32 partid = state->default_closid;
- u32 pmg = state->default_rmid;
+ u64 partid = state->default_closid;
+ u64 pmg = state->default_rmid;
/*
* If this task has a closid/rmid assigned, use it.
@@ -73,20 +73,20 @@ static void __mpam_sched_in(void)
/* set in EL0 */
reg = mpam_read_sysreg_s(SYS_MPAM0_EL1, "SYS_MPAM0_EL1");
- reg = reg & (~PARTID_MASK) & partid;
- reg = reg & (~PMG_MASK) & pmg;
+ reg = PARTID_SET(reg, partid);
+ reg = PMG_SET(reg, pmg);
mpam_write_sysreg_s(reg, SYS_MPAM0_EL1, "SYS_MPAM0_EL1");
/* set in EL1 */
reg = mpam_read_sysreg_s(SYS_MPAM1_EL1, "SYS_MPAM1_EL1");
- reg = reg & (~PARTID_MASK) & partid;
- reg = reg & (~PMG_MASK) & pmg;
+ reg = PARTID_SET(reg, partid);
+ reg = PMG_SET(reg, pmg);
mpam_write_sysreg_s(reg, SYS_MPAM1_EL1, "SYS_MPAM1_EL1");
- /* set in EL2 */
+ /* [FIXME] set in EL2 (hard code for VHE enabed) */
reg = mpam_read_sysreg_s(SYS_MPAM2_EL2, "SYS_MPAM2_EL2");
- reg = reg & (~PARTID_MASK) & partid;
- reg = reg & (~PMG_MASK) & pmg;
+ reg = PARTID_SET(reg, partid);
+ reg = PMG_SET(reg, pmg);
mpam_write_sysreg_s(reg, SYS_MPAM2_EL2, "SYS_MPAM2_EL2");
}
}
--
2.31.0